发明名称 NON-VOLATILE MEMORY AND METHOD WITH BIT LINE TO BIT LINE COUPLED COMPENSATION
摘要 When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.
申请公布号 KR20060067970(A) 申请公布日期 2006.06.20
申请号 KR20067005471 申请日期 2006.03.17
申请人 发明人
分类号 G11C16/12;G11C11/56;G11C16/04;G11C16/06;G11C16/24;G11C16/34 主分类号 G11C16/12
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