| 摘要 |
A clock generating circuit and a display device having the same are provided. An exemplary clock generating circuit includes a first voltage generating part, a second voltage generating part and an intermediate voltage generating part. The first voltage generating part generates a first voltage during a high level period. The second voltage generating part generates a second voltage that is lower than the first voltage during a low level period. The intermediate voltage generating part generates an intermediate voltage that is higher than the second voltage and lower than the first voltage during a first transition period when the second voltage is changed to the first voltage and a second transition period when the first voltage is changed to the second voltage.
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