| 摘要 |
PROBLEM TO BE SOLVED: To provide a processor having a plurality of instruction sets that facilitates switching of instruction sets. SOLUTION: The processor 100(1) comprises a first decoder 116 for decoding instructions included in an instruction set A, a second decoder 118 for decoding instructions included in an instruction set B, a register file A 134 for the instruction set A, a register file B 135 for the instruction set B, and a shared register file 136. COPYRIGHT: (C)2006,JPO&NCIPI
|
