发明名称 PROCESSOR AND ARITHMETIC PROCESSING METHOD
摘要 PROBLEM TO BE SOLVED: To reduce the number of gates in a register and efficiently process a plurality of tasks or threads in a processor for pipeline processing. SOLUTION: A pipeline processor 1 is provided with a memory 100 for a register comprised of memories instead of register files, as well as a memory 30 for a program counter comprised of memories instead of registers constituting a PC. Therefore, when compared with a case in which the memories are comprised of registers, the number of gates in the register can be reduced, and the context can be switched by specifying an address without exchanging the context, so that a plurality of tasks or threads can be efficiently processed. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006139645(A) 申请公布日期 2006.06.01
申请号 JP20040330087 申请日期 2004.11.15
申请人 SEIKO EPSON CORP 发明人 SHIRAI MASAKAZU
分类号 G06F9/48;G06F9/34;G06F9/38 主分类号 G06F9/48
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