| 摘要 |
A Newton's method-based timing recovery circuit includes a sampling clock generator, a sampler, an interpolator, a timing error detector for generator a timing error signal, a third delayer, a second subtractor, a rightward-bit-shifter, a multiplexer, a leftward-bit-shifter for leftward shifting a differential timing error signal, a fourth delayer, a first comparator, an incrementing/decrementing device, a first delayer, and a second comparator for comparing the differential timing error signal with the timing error signal and for controlling the incrementing/decrementing device to increment/decrement a timing_offset signal.
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