| 摘要 |
According to the invention, means for reducing the interference caused by a voltage or a current in common mode, comprise adders (S 3 ; S 4 ) in each path for adding a first counter-reaction voltage (V 1 ) to the voltage of the relevant path, a bridge (R 1 , R 2 ) and an inverter (I 3 ) for provision of said first counter-reaction voltage which is equal to half the sum of the voltages (VA, VB), respectively supplied to the inputs (A; B), with an opposing sign. According to the invention, the effect of a delay introduced by the inverter (I 3 ) may be reduced, whereby said stage further comprises means (S 5 ; S 6 ) for adding in addition to the input voltage for each path, a second counter-reaction voltage (Va 1 ; Vb 1 ), and means (R 1 , R 2 , I 1 , S 1 ; I 2 , S 2 ) for provision of a second counter-reaction voltage (Va 1 ; Vb 1 ) which is a function of the input voltage (VA; VB) at the input corresponding to said path, with an opposing sign and with a delay identical to that generated by the inverter (I 3 ).
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