发明名称 Method for forming bit line
摘要 A method for forming a bit line. A semiconductor substrate is provided. A MOS having a gate and an S/D area is formed on the semiconductor substrate. A first dielectric layer with a first opening is formed on the semiconductor substrate to expose the S/D area. A conducting layer is formed in the first opening. A barrier layer is formed on the surface of the first dielectric layer and the conducting layer. A second dielectric layer having a second opening and a third opening is formed on the barrier layer, the position of the second opening corresponding to the first opening. Metal layers are formed in the second opening and the third opening as bit lines, respectively.
申请公布号 US7052949(B2) 申请公布日期 2006.05.30
申请号 US20030459327 申请日期 2003.06.11
申请人 NANYA TECHNOLOGY CORPORATION 发明人 WU KUO-CHIEN;HUANG TSE-YAO;CHEN YI-NAN
分类号 H01L21/4763;H01L21/768;H01L21/8238;H01L21/8242 主分类号 H01L21/4763
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