发明名称 |
Method for optimizing digital arithmetic circuit e.g. for industrial digital circuit design, involves initially describing circuit behavior with arithmetic one-bit operations |
摘要 |
<p>A method for optimizing a digital arithmetic circuit in which the digital arithmetic circuit is described by an arithmetic bit-plane description which describes the behavior of the circuit with arithmetic 1-bit-operations and in which the arithmetic bit-plane description is optimized with a previously established set of conversion rules for such a length of time, until none of the conversion rules in the previously established set of defined conversion rules any longer leads to an optimization of the arithmetic bit-plane description. Independent claims are included for the following (1) a method for properties testing of a digital arithmetic circuit; (2) a device for optimizing a digital arithmetic circuit; (3) a computer program product with computer program and; (4) an electronic readable data carrier.</p> |
申请公布号 |
DE102004055730(A1) |
申请公布日期 |
2006.05.24 |
申请号 |
DE20041055730 |
申请日期 |
2004.11.18 |
申请人 |
INFINEON TECHNOLOGIES AG |
发明人 |
WEDLER, MARKUS;STOFFEL, DOMINIK;KUNZ, WOLFGANG;BRINKMANN, RAIK |
分类号 |
G06F17/50;G06F7/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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