发明名称 |
Edge termination for silicon power devices |
摘要 |
<p>A silicon semiconductor die comprises a heavily doped silicon substrate (701) and an upper layer (702) comprising doped silicon of a first conduction type disposed on the substrate (701). The upper layer comprises a well region (703) of a second, opposite conduction type adjacent an edge termination zone (705) that comprises a layer of a material having a higher critical electric field than silicon. Both the well region (703) and adjacent edge termination zone (705) are disposed at an upper surface of the upper layer, and an oxide layer (706) overlies the upper layer and the edge termination zone. The invention also concerns a process for forming a silicon die having edge termination. <IMAGE></p> |
申请公布号 |
EP1065727(B1) |
申请公布日期 |
2006.05.24 |
申请号 |
EP20000401826 |
申请日期 |
2000.06.27 |
申请人 |
INTERSIL CORPORATION |
发明人 |
ZENG, JUN;DOLRY, GARY;MURALEEDHARAN, PRAVEEN |
分类号 |
H01L29/06;H01L29/78;H01L21/04;H01L21/336;H01L29/12;H01L29/24;H01L29/267 |
主分类号 |
H01L29/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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