PASS THROUGH DEBUG PORT ON A HIGH SPEED ASYNCHRONOUS LINK
摘要
An example computer system includes a first bridge device that includes an interface controller. The interface controller combines debug information generated within the bridge device with a training pattern. The first bridge device is coupled to a second bridge device via a high-speed asynchronous interconnect. The first bridge device converts the debug information and training pattern into a packet to be transmitted over the interconnect to the second bridge device. The training pattern serves to allow the second bridge device to maintain bit and symbol synchronization during the transfer of the debug information.
申请公布号
WO2005066813(A3)
申请公布日期
2006.05.18
申请号
WO2004US43736
申请日期
2004.12.22
申请人
INTEL CORPORATION;GUPTA, ASHISH;FAHIM, BAHAA;DICKEY, KENT;JASPER, JONATHAN
发明人
GUPTA, ASHISH;FAHIM, BAHAA;DICKEY, KENT;JASPER, JONATHAN