| 摘要 |
A semiconductor device includes a timing correction circuit coupled to an external terminal for receiving an input data signal to change a relative timing between the input data signal and an internal clock signal to generate a plurality of relative latch timings to latch one of the input data signal and the internal clock signal in response to the other one of the input data signal and the internal clock signal, thereby selecting an optimal relative latch timing according to a result of the latching, and a latch circuit coupled to the timing correction circuit to latch the input data signal with the optimal relative latch timing.
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