发明名称 SEMICONDUCTOR MEMORY
摘要 <p>A memory cell array (1) includes a plurality of memory cells arranged in a matrix and storing data by use of n values exhibiting first, second through n-th states (where n is a natural number equal to or greater than two). Before performing a write operation for storing data into a first memory cell of the memory cell array, a control circuit performs, if at least a second memory cell adjacent to the first memory cell exhibiting the first state and not having reached a first threshold voltage, a write operation to the second memory cell until the first threshold voltage is reached.</p>
申请公布号 WO2006051917(A1) 申请公布日期 2006.05.18
申请号 WO2005JP20748 申请日期 2005.11.11
申请人 KABUSHIKI KAISHA TOSHIBA;SHIBATA, NOBORU;KANEBAKO, KAZUNORI 发明人 SHIBATA, NOBORU;KANEBAKO, KAZUNORI
分类号 G11C16/10 主分类号 G11C16/10
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