发明名称 |
All-digital clock recovery using a fractional divider |
摘要 |
<p>A method and an improved apparatus for clock recovery from data streams containing embedded reference clock values controlled clock source includes of a controllable digital fractional divider receiving a control value from digital comparator and a clock input from a digital clock synthesizer driven by a fixed oscillator.</p> |
申请公布号 |
EP1324619(B1) |
申请公布日期 |
2006.05.17 |
申请号 |
EP20020022752 |
申请日期 |
2002.10.11 |
申请人 |
STMICROELECTRONICS PVT. LTD |
发明人 |
CHAKRAVARTHY, KALYANA |
分类号 |
H03L7/00;H03L7/099;H03L7/181;H03L7/197;H04N5/12;H04N7/56;H04N21/43 |
主分类号 |
H03L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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