| 摘要 |
A data processing apparatus that reduces a fanout load of a control signal for controlling a pipeline includes a first pipeline processing portion for executing a processing in five divided stages, a second pipeline processing portion for executing a processing one stage behind the first pipeline processing portion, and a plurality of flip-flops for latching the control signals inputted to the respective stages. The second pipeline processing portion performs the processing in each stage based on delayed control signals generated by once latching the control signals inputted to the respective stages by the flip-flop, thereby reducing the fanout load and signal delay of the control signals. Moreover, a wiring length of a control line for transmitting the control signals can be set to be longer than a conventional wiring length.
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