| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To realize the duty ratio of 50% even in the terminal of the clock distribution network of LSI. <P>SOLUTION: A clock S0 to be controlled is inputted to an inverter INV1 composed of pMOS Q1 and Q2 and nMOS Q3 and Q4. A control clock S1 is inputted to the gate of a pMOS Q5 connected between a power source and the output terminal of the INV1. S1 is a clock with its phase delayed than that of S0. When S0 is changed to high but S1 is still low, a voltage modulation clock SS0 is set to be higher than the threshold of the inverter INV1. Therefore, at such a time, the level of an adjusted clock S2 is still low. When S0 is changed to low, S2 becomes low as well. Therefore, as the adjusted clock S2, a clock matching its rise edge to S1 and matching its fall edge to S0 can be obtained. A clock thus obtained is supplied to the LSI. <P>COPYRIGHT: (C)2003,JPO</p> |
