Data transfer control device

摘要

Even when an S-PCI bus 1 b requests transfer while a P-PCI bus 1 a is executing burst transfer, assert of a TRDY# signal for data transfer of the P-PCI side is delayed so that next data transfer of the P-PCI side is completed within 8 clock cycles since the TRDY# signal for data transfer of the P-PCI side is asserted.