发明名称 |
Multi-clock domain data input-processing device having clock-receiving locked loop and clock signal input method thereof |
摘要 |
A multi-clock-domain data input processing device preferably includes: a clock-signal-receiving synchronous circuit that generates an output clocking signal by phase-delaying a first clock signal; a data input part having a delay locked loop (DLL); and an input-processing part. The data input part preferably inputs data in response to the first clock signal and the input-processing part transfers data in response to a second clock signal having a timing different from that of the first clock signal. A clock-signal applying method for operating the multi-clock-domain data input-processing device preferably includes the steps of: applying a plurality of clock signals to a signal-receiving clock conversion part; and applying a delayed clocking signal outputted from the DLL to the remaining parts of the data input-processing device.
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申请公布号 |
US7038971(B2) |
申请公布日期 |
2006.05.02 |
申请号 |
US20020288540 |
申请日期 |
2002.11.06 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
CHUNG DAE-HYUN |
分类号 |
G11C8/00;G11C11/4096;G06F5/06;G11C7/10;H03L7/081;H04L7/00;H04L7/02 |
主分类号 |
G11C8/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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