发明名称 |
Methods and apparatuses for detecting clock loss in a phase-locked loop |
摘要 |
Embodiments of the present invention describe methods and apparatuses for detecting signal loss in circuits such as a phase-locked loop (PLL). In one embodiment a PLL is equipped with detection logic to detect loss of a reference clock provided to the PLL and a feedback clock generated by the PLL.
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申请公布号 |
US7038508(B2) |
申请公布日期 |
2006.05.02 |
申请号 |
US20040836645 |
申请日期 |
2004.04.30 |
申请人 |
INTEL CORPORATION |
发明人 |
PARKER RACHAEL J.;LAW HON-MO RAYMOND;LOW TIMOTHY D. |
分类号 |
H03L7/06;H03L7/00;H03L7/08;H03L7/089 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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