| 摘要 |
A method and apparatus are provided for processing repeat string instructions with increased efficiency in a processor pipeline. Rather than explicitly generating an initial count register setup micro instruction each time a repeat (REP) prefix in encountered, the processor includes a shadow ECX register operating in parallel with an architectural ECX count register. This enables the contents of the architectural ECX register, which are also stored in the shadow ECX register, to be immediately transferred to an internal count register from the shadow ECX register upon the first iteration of a repeat string micro code sequence.
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