Tester system having multiple instruction memories

摘要

An apparatus for testing an integrated circuit includes a sequence control logic unit having an output channel connectable to an input pin of a device under test, a first memory to store a first instruction set comprising instructions executable by the sequence control logic unit, and a second memory to store a second instruction set comprising instructions executable by the sequence control logic unit, wherein at least one of the first memory and the second memory comprises a memory accessible in a non-sequential fashion.