| 摘要 |
<P>PROBLEM TO BE SOLVED: To decrease the amount of electric charges injected into a floating gate region, by constituting the floating gate region using quantum thin lines of nanometer size and arranging it, such that it intersects with the arrangement direction of the source region and the drain region. <P>SOLUTION: At substantially the center of a region 143 of the shape of a rectangle formed on a silicon substrate 141, in a substantially the right-angle direction relative to the longitudinal direction of the region 143, a quantum thin line 145 of nanometer size is formed and set as a floating gate region. Then, a nonvolatile memory, in which the floating gate region between a channel region 150 and a gate electrode 147 is constituted using the quantum thin line 145, is formed by forming the gate electrode 147, a source region 148, and a drain region 149. At this time, the quantum thin line 145 is arranged, such that it intersects at substantially a right-angle with the source region 148 and the drain region 149. Accordingly, it is possible to reduce the stored electric charges in the floating gate region and implement a nonvolatile memory having very low power dissipation, ultra-high density, and large capacity. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
