发明名称 |
CMOS circuits with protection for a single event upset |
摘要 |
A dual structure is introduced to the transistor in a flip-flop or a data input step controlled by a clock of a semiconductor logic circuit. The dual structure is formed by connecting a transistor with a MOS transistor having a channel of the same conductivity type in series with respect to the line of a source or drain and connecting their gates to each other, or by connecting an inverter with p-MOS transistors, one for VDD side and one for VSS side of the output step. The dual structure prevents single event phenomenon in a semiconductor logic circuit, such as inverter, SRAM and data latch circuit. <IMAGE> |
申请公布号 |
EP1533901(A3) |
申请公布日期 |
2006.04.19 |
申请号 |
EP20050000654 |
申请日期 |
2003.03.03 |
申请人 |
NATIONAL SPACE DEVELOPMENT AGENCY OF JAPAN |
发明人 |
MATSUDA, SUMIO;KUBOYAMA, SATOSHI;DEGUCHI, YASUSHI |
分类号 |
G11C11/41;H03K19/003;G11C11/412;H01L21/8244;H01L27/02;H01L27/10;H01L27/11;H03K3/037;H03K3/356;H03K19/0948 |
主分类号 |
G11C11/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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