发明名称 |
Floating-body DRAM using write word line for increased retention time |
摘要 |
A DRAM memory cell uses a single transistor to perform the data storage and switching functions of a conventional cell. The transistor has a floating channel body which stores a potential that corresponds to one of two digital data values. The transistor further includes a gate connected to a first word line, a drain connected to a second word line, and a source connected to a bit line. By setting the word and bit lines to specific voltage states, the channel body stores a digital one potential as a result of impact ionization and a digital zero value as a result of forward bias of body-to-source junction.
|
申请公布号 |
US7031203(B2) |
申请公布日期 |
2006.04.18 |
申请号 |
US20050066395 |
申请日期 |
2005.02.28 |
申请人 |
INTEL CORPORATION |
发明人 |
TANG STEPHEN;KESHAVARZI ALI;SOMASEKHAR DINESH;PAILLET FABRICE;KHELLAH MUHAMMAD;YE YIBIN;DE VIVEK |
分类号 |
G11C5/14;G11C11/404;G11C11/408;H01L27/108;H01L29/78 |
主分类号 |
G11C5/14 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|