| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a frequency synthesizer which is capable of shortening a lockup time and reducing power consumption simultaneously by reducing the lower limit of the setting range of the total number of division frequencies and increasing a reference frequency, while keeping the modulus of a prescaler high. <P>SOLUTION: An oscillation frequency (fv) is adjusted by a VCO (3) in accordance with control signals (Vf) generated by a phase comparator (1), a charge pump (5), and an LPF (2) corresponding to a phase difference between a reference signal (fr) and a comparison signal (fd). The prescaler (6) subjects the output signal (fv) of the VCO (3) to frequency division processing with a constant modulus äselected from (k+2) integers in accordance with mode signals (S, S1, S2, to Sk)}. Output pulses (fc) of the prescaler (6) are counted by a main counter (7) to the number (N) of division frequencies, and (k+1) swallow counters (8 and 9) count successively up to the number of discrimination circuits (A<SB>0</SB>, A<SB>1</SB>, etc). A mode control unit (10) switches the mode signals (S, S1 to Sk) from one to the other in accordance with output signals of the counters (7, 8, and 9). <P>COPYRIGHT: (C)2006,JPO&NCIPI |
