Method for reducing the evaluation outlay in the monitoring of layout changes for semiconductor chips

摘要

In a method for monitoring layout changes for semiconductor chips, a first group of error data is generated by comparing a first layout with wiring and layout rules. A second group of error data is generated by comparing a second layout with the wiring and layout rules, the second layout being generated from layout changes of the first layout. The first group of error data is compared to the second group of error data and only error data that are different in the first and second groups is output for evaluation.