| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce the power consumption of a dynamic type semiconductor storage device, or to increase the speed thereof. <P>SOLUTION: Different sub decode signals are supplied to respective blocks BL<SB>1</SB>-BL<SB>m</SB>, constituting a memory cell array. The sub decode signals are generated by sub decode signal generating circuits SDB1<SB>1</SB>-SDB1<SB>m</SB>, provided corresponding to respective blocks BL<SB>1</SB>-BL<SB>m</SB>, from block selection addresses BS<SB>1</SB>-BS<SB>m</SB>provided to the blocks, respectively, and addresses SDA<SB>1</SB>and SDA<SB>2</SB>for the sub decode signals. The sub decode signals are supplied to only the sub decode circuits of one block of designated by the block selection addresses, and the number of sub decode circuits and the length of a signal line, carried by one sub decode signal generation circuit, can be reduced. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
