| 摘要 |
PROBLEM TO BE SOLVED: To provide a logic equivalence verification system having high verification efficiency in which information collection applied to an evaluation verification tool and the collection of HDL files configuring a logical hierarchy for executing verification for a largely scaled LSI are automated, and divided into verifiable units, thus verification is automatically executed. SOLUTION: The logic equivalence verification system is provided with a logic synthesis processing part 301 for performing the logic synthesis of a plurality of HDL files to generate a gate circuit and a logic equivalence verification processing part 302 for comparing a reference logic circuit constituted of the plurality of HDL files with a comparison object logic circuit constituted of a gate circuit formed by performing the logic composition of the plurality of HDL files, and for verifying logic equivalence. The logic equivalence verification processing part 302 is operated while being interlocked with the logic composition processing part 301 to receive in real time the information of a logical hierarchy whose logic change or addition has been performed by the logic synthesis processing part 301, and assembles the logic hierarchy by retrieving the HDL files necessary for the reference logic circuit, and divides and executes the logic equivalence verification with the comparison object logic circuit. COPYRIGHT: (C)2006,JPO&NCIPI
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