| 摘要 |
1,046,357. Data store address selection. STANDARD TELEPHONES & CABLES Ltd. Oct. 30, 1964 [Nov. 6, 1963], No. 44310/64. Headings G4A and G4C. In an arrangement for selecting addresses in a matrix memory, certain ones of the memory rows store indicator words, each indicator word corresponding to a number of storage rows equal to the number of " 1 " bits stored in the row so that a storage row can be selected by first selecting an indicator word then selecting one of the bit positions storing a " 1 " in that word and hence selecting the desired storage row. The arrangement is applicable to a computer programme interrupt system in which each indicator row of the matrix corresponds to a device which may request an interrupt and bit positions in that row store a " 1 " in accordance with the various reasons for which an interrupt is desired. Since each device may have only a relatively small number of interrupt reasons, i.e. there are only a relatively small number of " 1 "s in each indicator row with the same relatively small number of storage rows, an economy in the selection arrangements is achieved, but the system is readily expandable by adding extra storage rows and corresponding " 1 " bits in indicator rows. The data extracted from the storage row may be used to address the computer programme memory. Fig. 1 (not shown) shows a matrix MM consisting of m indicator rows only. To select an address, an " address word " consisting of two parts is entered into registers AR1, AR2 for the two parts respectively. The contents of the first part in AR1 causes an indicator word to be read out and stored in a p-bit register SD1. The second part in AR2 is translated at Tr to enter in a p-bit register SD2 a p-bit word consisting of all " 0 "s except for a single " 1 " bit corresponding to the desired storage row (not shown). The contents of registers SD1, SD2 are now left shifted, the successive bits being compared in coincidence gates G1-G4. For each detection of a " 1 " in register SD1 corresponding to a " 0 " in register SD2, a " 1 " is added to the contents of the register AR1 (which is a binary counter) this process being continued until the " 1 " in register SD2 is reached. The thus modified contents of the register AR1 is now employed to select the desired storage row (not shown). Various improper conditions, such as the correspondence of the " 1 " in register SD2 to a " 0 " in register SD1 cause an error signal to be produced. The storage rows (not shown) may be part of the matrix MM or may constitute a separate matrix. The matrix MM may be a semi-permanent capacitative store. In a second embodiment (Fig. 2, not shown), the stages A1 to Ap of the register SD1 are not shifted but are translated successively to the code of the register AR2 for comparison. |
