| 摘要 |
PROBLEM TO BE SOLVED: To obtain an efficient layout and to miniaturize a semiconductor device by effectively verifying the layout so as to prevent antenna damage. SOLUTION: A layout verification method comprises an interval acquisition step (S401) for defining wiring connected through a via to a gate as the wiring under consideration and acquiring an interval between the wiring under consideration and wiring adjacent to it; computation steps (S402-S404) for computing an antenna ratio corresponding to the interval between the wiring under consideration and the adjacent wiring, the area of the gate and the area of the wiring under consideration; and an output step (S404) for outputting antenna damage errors, when the antenna ratio exceeds a prescribed value. COPYRIGHT: (C)2006,JPO&NCIPI
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