| 摘要 |
PROBLEM TO BE SOLVED: To provide a gate array integrated circuit which is a part of a semiconductor integrated circuit for realizing improvement in the microfabrication and an yield and its layout method. SOLUTION: For the gate array integrated circuit, the base layer of a unit cell 10 for connecting a PMOS transistor 12 and an NMOS transistor 14 via polysilicons 16 and 18 is constituted, a plurality of gate terminal regions 34 included in the polysilicons 16 and 18 are pulled out in the horizontal direction; and two or more contacts or through-holes are arranged in the respective gate terminal regions 34. Thus, wiring efficiency is improved, and the microfabrication and yield of the gate array integrated circuit are improved. COPYRIGHT: (C)2006,JPO&NCIPI
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