Circuit path examining method for integrated circuit application, involves examining timing performance of circuit path as correct/incorrect, respectively, if pair of setup and hold time does not make/makes timing violation

摘要

The method involves identifying a timing performance of a circuit path to be examined, as correct, if a pair of a set up and holding time from several pairs, does not make a timing violation. The timing performance is identified as incorrect, if the pair of setup and holding time from the several pairs makes a timing violation. A pair with shortest possible set up time is determined as set up time and holding time for the path. An independent claim is also included for a device for examining a circuit path.