发明名称 Delay circuit that scales with clock cycle time
摘要 A circuit having a process, voltage, and temperature (PVT) invariant delay element is disclosed. In one embodiment, the present invention includes a first and second operational transconductance amplifier (OTA), a first and second switched capacitor driven by a clock, and a first and second clock-controlled switch. In addition, the present invention includes a trip inverter, a delay inverter, and a plurality of transistors. In so coupling the first and second OTA, the first and second switched capacitor, the first and second clock-controlled switch, the trip inverter, the delay inverter, and the plurality of transistors, a circuit having a PVT invariant delay element is provided.
申请公布号 US7019576(B1) 申请公布日期 2006.03.28
申请号 US20040804988 申请日期 2004.03.18
申请人 CYPRESS SEMICONDUCTOR CORPORATION 发明人 SANCHETI SANJAY K.;CHEN SUWEI
分类号 H03H11/26 主分类号 H03H11/26
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