发明名称 Process for designing comparators and adders of small depth
摘要 Logic circuits for logical operations, based on a function f<SUB>N</SUB>=x<SUB>1 </SUB>OR (x<SUB>2 </SUB>AND (x<SUB>3 </SUB>OR (x<SUB>4 </SUB>AND . . . x<SUB>N </SUB>. . . ))) or f'<SUB>N</SUB>=x<SUB>1 </SUB>AND (x<SUB>2 </SUB>OR (x<SUB>3 </SUB>AND (x<SUB>4 </SUB>OR . . . x<SUB>N </SUB>. . . ))), are designed by defining a top portion of the logic circuit based on a pre-selected pattern of 2-input $ and @ gates. The top portion has N inputs and approximately N/3 outputs. A smaller logic circuit is defined having approximately N/3 inputs coupled to the outputs of the top portion. In one embodiment, the circuit is designed for a circuit having N' inputs, where N' is 3<SUP>n </SUP>or 2*3<SUP>n</SUP>, and the N'-N most significant inputs are set to fixed values. The extra gates are removed resulting in a minimum depth circuit. In another embodiment, the depth is further reduced in some cases by designing a circuit for N-1 inputs and transforming the circuit to an N-input circuit. The $ and @ gates are converted to AND and/or OR gates, depending on the function.
申请公布号 US7020865(B2) 申请公布日期 2006.03.28
申请号 US20030602570 申请日期 2003.06.24
申请人 LSI LOGIC CORPORATION 发明人 GRINCHUK MIKHAIL I.;BOLOTOV ANATOLI A.
分类号 G06F17/50 主分类号 G06F17/50
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