| 摘要 |
An internal clock generator comprises delay units adapted and configured to delay a first clock outputted from a clock buffer for predetermined delay times to output a plurality of second clocks, respectively, clock pulse generating units adapted and configured to generate clock pulses depending on the plurality of second clocks, respectively and a clock synthesizer adapted and configured to synthesize the clock pulses to generate an internal clock. As a result, a clock frequency of test equipment is internally increased at a wafer level test mode, thereby performing a high-speed test and reducing a test cost.
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