发明名称 |
Digital delay buffers and related methods |
摘要 |
<p>A digital delay buffer may be provided with both a fast processing, small capacity memory section and a slow processing, large capacity memory section. The use of two memory sections allows the buffer to generate an aligned data stream with n-bit block level latencies from a plurality of delayed data portions, even if one of the portions is subjected to an undue delay.
</p> |
申请公布号 |
EP1624601(A3) |
申请公布日期 |
2006.03.22 |
申请号 |
EP20050254818 |
申请日期 |
2005.08.02 |
申请人 |
LUCENT TECHNOLOGIES INC. |
发明人 |
BASKARAN, NARAYANAN;DIPASQUALE, RICHARD J.;TOWNE, JEFFREY ROBERT;TURNER, GARY A. |
分类号 |
H04J3/06;G06F12/00;G11C7/00;H04L29/06 |
主分类号 |
H04J3/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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