发明名称 |
Designing a semiconductor device layout using polishing regions |
摘要 |
Designing method of an electronic device subjected to a chemical mechanical polishing process in a fabrication process thereof is conducted according to the steps of: dividing a substrate surface into first sub-regions; optimizing a coverage ratio of hard-to-polish regions in the first sub-regions to fall in a first predetermined range corresponding to the first sub-regions; dividing the substrate surface into second sub-regions different from the first sub-regions; and optimizing a coverage ratio of the hard-to-polish regions in the second sub-regions to fall in a second predetermined range corresponding to the second sub-regions, wherein patterns having a shorter edge of 5 mum or less are excluded from the optimization.
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申请公布号 |
US7017133(B2) |
申请公布日期 |
2006.03.21 |
申请号 |
US20040849368 |
申请日期 |
2004.05.20 |
申请人 |
FUJITSU LIMITED |
发明人 |
IDANI NAOKI;KARASAWA TOSHIYUKI;NANJO RYOTA |
分类号 |
G06F17/50;H01L21/76;H01L21/304;H01L21/3105;H01L21/3205;H01L21/82;H01L21/822;H01L27/04 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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