发明名称 Interconnect routing using parallel lines and method of manufacture
摘要 The subject invention is a system, apparatus and/or method of forming interconnects on a semiconductor wafer. Particularly, the subject invention provides interconnect routing using parallel lines on a semiconductor wafer. The method includes producing a plurality of spaced, parallel interconnects on a wafer, and producing interruptions in selective ones of the plurality of interconnects where the connection should be disrupted. Preferably, the plurality of spaced, parallel lines are formed over the entire die region of the wafer and are spaced from one another by a predetermined width. In one form, a mask having a plurality of spaced, parallel lines may be used.
申请公布号 US7014957(B1) 申请公布日期 2006.03.21
申请号 US20020335470 申请日期 2002.12.31
申请人 LSI LOGIC CORPORATION 发明人 ZARKESH-HA PAYMEN;DONIGER KENNETH J;LOH WILLIAM M.
分类号 G03F9/00 主分类号 G03F9/00
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