<p>A power semiconductor device comprising an array of cells distributed over a surface of a substrate (62), the source regions (37) of the individual cells of the array comprising a plurality of source region branches (80) each extending laterally outwards towards at least one source region branch (80) of an adjacent cell and presenting juxtaposed ends, the base regions (36) of the individual cells of the array comprising a corresponding plurality of base region branches merging together adjacent and between the juxtaposed ends of the source region branches (80) to form a single base region surrounding the source regions (37) of the individual cells of the array in the substrate. The junctions between the merged base region (36) and the drain region are solely concave laterally and define rounded current conduction path areas (39) for the on-state of the device between adjacent cells that are depleted in the off-state of the device to block flow of current from the source regions (37) to the drain electrode (83). Floating voltage regions (102) of opposite conductivity type to the drain region are buried in the substrate (62) beneath the merged base region (36) and present features (104) corresponding to and juxtaposed with features of the merged base region (36) in each cell so that the voltage of the floating voltage regions (102) tends to the voltage of the source regions (37) when depletion layers blocking the current conduction paths reach the floating voltage regions (102), whereby to enhance the development of the depletion layers. The features (104) of the floating voltage regions define rings of the opposite conductivity type to the drain region that surround the current conduction paths (39) of respective cells. The floating voltage regions (102) include respective islands (106) situated within the current conduction paths (39).</p>
