| 摘要 |
PROBLEM TO BE SOLVED: To provide a stack via layout design method which can previously prevent reduction of a reliability caused by the thermal stress distortion of a stack via in multilayered wiring using an interlayer film material having a low dielectric constant, and also to provide a semiconductor device. SOLUTION: A dangerous stack via having a high failure occurrence possibility caused by a distortion from a temperature change is extracted based on a specific stack via structure from a stack via design layout result, the distortion of the dagerous stack via from the temperature change is calculated to extract a critical stack via exceeding a predetermined critical distortion, the distortion of the critical stack via is reduced by additionally arranging a new via structure so as not to cause a circuit function to be changed in a region including the critical stack via exceeding the critical distortion, thus obtaining a layout result of stack vias having a high reliability. Moreover, such a semiconductor device is provided as constituted without the specific stack via. COPYRIGHT: (C)2006,JPO&NCIPI
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