Decimal floating-point adder

摘要

A decimal floating-point adder is described that performs addition and subtraction on decimal floating-point operands. The decimal floating-point adder includes an alignment unit that receives a first floating-point number and a second floating-point number, and aligns significands associated with the floating-point numbers such that exponents associated with the floating-point numbers have equal values. The decimal-floating-point adder further includes a binary adder that adds the aligned significands. The floating-point adder includes a correction unit and an output conversion unit to produce a final resultant decimal floating-point number. The decimal floating-point adder may be pipelined so that complete resultant decimal floating-point numbers may be output each clock cycle.