发明名称 |
Precision bypass clock for high speed testing of a data processor |
摘要 |
A system clock circuit that provides a high-speed reference clock signal for operating an integrated circuit. The system clock circuit comprises a frequency combiner circuit that receives a first external clock signal having a frequency F1 and a second external clock signal having frequency F2, where F2 is an integer multiple of F1. The second external clock signal is phase-shifted by P degrees with respect to the first external clock signal. The frequency combiner circuit generates from the first and second external clock signals a first output clock signal having an operating frequency that is the sum of F1 and F2. The system clock circuit also comprises a clock selection circuit that selectively applies the first output clock signal to the integrated circuit.
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申请公布号 |
US7007188(B1) |
申请公布日期 |
2006.02.28 |
申请号 |
US20030426049 |
申请日期 |
2003.04.29 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
TISCHLER BRETT A.;KOMMRUSCH STEVEN J. |
分类号 |
G06F1/04 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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