发明名称 Interactive circuit assembly test/inspection scheduling
摘要 Systems and methods for scheduling circuit assemblies for inspection in an electronics manufacturing environment are provided. One embodiment comprises an interactive system for scheduling circuit assemblies for inspection. Briefly described, one such system comprises: a data structure residing in memory and comprising a plurality of data elements that define the order in which a plurality of circuit assemblies are scheduled to be inspected, each data element comprising a reference to one of the plurality of circuit assemblies; logic configured to control the manner in which the plurality of circuit assemblies are scheduled for inspection based on the data structure; and logic configured to enable a user to modify the data structure.
申请公布号 US7007206(B2) 申请公布日期 2006.02.28
申请号 US20020156280 申请日期 2002.05.28
申请人 AGILENT TECHNOLOGIES, INC. 发明人 ANONSON STEVE
分类号 G06F11/30;G06F11/00 主分类号 G06F11/30
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