| 摘要 |
<p>A processor for encrypting or decrypting information to be communicated from a first location to a second location, the processor being operable in at least two modes including (i) a first mode wherein information is encrypted by an encryption portion of a keystream and a synchronisation indicator is generated in association with each encryption portion and (ii) a second mode wherein information is encrypted by a plurality of encryption portions and a single synchronisation indicator is generated in association with each plurality of encryption portions.</p> |
