| 摘要 |
A data processor comprises a plurality of processing elements (PEs) 1, with memory 3 local to at least one of the processing elements, and a data packet-switched network 2 interconnecting the processing elements and the memory to enable any of the PEs to access the memory. The network consists of nodes 2 arranged linearly or in a grid, eg in a SIMD array, so as to connect the PEs and their local memories to a common controller 10. Transaction-enabled PEs and nodes set flags "E" or "T", which are maintained untie the transaction is completed and signal status to the co_troller, eg over a series of OR-gates 13. The processor performs memory accesses on data stored in the memory in response to control signals sent by the controller to the memory. The local memories share the same memory map or space. External memory may also be connected to "end" nodes interfacing with the network, eg to provide cache. One or more further processors may similarly be connected to the network so that all the PE memories from all the processors share the same memory map or space. The packet-switched network supports multiple concurrent transfers between PEs and memory. Memory accesses include block and/or broadcast read and write operations, in which data can be replicated within the nodes and, according to the operation, written into the shared memory or into the local PE memory. |
