| 摘要 |
PROBLEM TO BE SOLVED: To provide a receiver and a transmitter whereby a delay due to relaying is reduced and the signal quality is enhanced by minimizing the delay caused when fast Fourier transform processing and inverse fast Fourier transform processing are executed. SOLUTION: A clock whose speed is a multiple of n (n is an integer of 2 or over) of a clock speed required for conventional FFT processing or IFFT processing is given to an FFT processing section 113 and an IFFT processing section 151 to carry out processing at a speed of a multiple of n. A RAM 114 is provided to a data input side of the FFT processing section 113, a RAM 115 is provided to a data output side, a RAM 152 is provided to a data input side of the IFFT processing section 151, a RAM 113 is provided to a data output side, so as to execute timing of data read/write synchronously or independently. COPYRIGHT: (C)2006,JPO&NCIPI |
