发明名称 PHASE-LOCKED LOOP CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide the configuration of a phase-locked loop circuit realizing improvement of carrier drawing-in characteristic by improving the carrier drawing-in characteristic in digital signal transmission. <P>SOLUTION: A phase-locked circuit is provided with a complex multiplier 71, a phase comparator 73, a loop filter 74, and a numerical value control oscillator 75 and the like. The phase comparator 73 is provided with a detected phase calculator 76 for acquiring an inverse tangent characteristic from a real part and an imaginary part of a complex signal to calculate the phase, and a phase error calculator 77 for obtaining each phase error between the phase of a neighborhood drawing points of two orthogonal digital phase modulations having different phase in a signal point arrangement pattern and the detected phase of a reception signal calculated above. Likelihood is obtained from square of phase error per pattern in each block, and the integration value of the phase error having high likelihood is outputted as a phase error. <P>COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006049984(A) 申请公布日期 2006.02.16
申请号 JP20040224197 申请日期 2004.07.30
申请人 NATIONAL INSTITUTE OF INFORMATION & COMMUNICATIONTECHNOLOGY 发明人 RI KANHOU;SARUWATARI NOBUFUMI;KARIYA NORIYUKI
分类号 H04L27/227;H03L7/08;H03L7/085;H03M13/25 主分类号 H04L27/227
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