| 摘要 |
PROBLEM TO BE SOLVED: To avoid the generation of a void in a formation prospective region of linearly arranged bit line contacts CB. SOLUTION: A semiconductor memory is loaded on a semiconductor chip 100; and has bit lines BL, source lines SL, and word lines WL that are perpendicular to the bit lines BL. The memory comprises: bit line side selector gate lines SGD and source line side selector gate lines SGS which are adjacent to both ends of the word line WL arranged in the bit line BL direction, and are arranged in parallel with the word line WL; a memory cell transistor MT arranged at the intersection of the bit line BL and the word line WL, and a selector gate transistor ST arranged at the intersection of the bit line BL and the selector gate line SGD; the bit line contacts CB arranged in the word line direction between the bit line side selector gate lines SGD; and a source line contact CS arranged in the word line direction between the source line side selector gates SGS, wherein an interval L1 between the bit line side selector gate lines SGD is larger than an interval L2 between the source line side selector gate lines SGS. COPYRIGHT: (C)2006,JPO&NCIPI
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