| 摘要 |
A parallel and pipelined radix - two to the fourth power FFT processor is provided to increase operation speed and data processing efficiency by using a structure of two parallel data paths, and a single path delay feedback structure. Multiple first butterfly operation units perform a butterfly operation when adding input signals. Multiple second butterfly operation units are connected with a following stage of the first butterfly operation units, and perform the butterfly operation to the data outputted from the first butterfly operation units. A parallel and pipelined radix - two to the fourth power FFT processor comprises the first and second butterfly operation units, and applies the radix - two to the fourth power FFT(Fast Fourier Transformation) algorithm.
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