Galois field multiplier array for use within a finite field arithmetic unit

摘要

A Galois field multiplier array includes a 1^st register, a 2^nd register, a 3^rd register, and a plurality of multiplier cells. The 1^st register stores bits of a 1^st operand. The 2^nd register stores bits of a 2^nd operand. The 3^rd register stores bits of a generating polynomial that corresponds to one of a plurality of applications (e.g., FEC, CRC, Reed Solomon, et cetera). The plurality of multiplier cells is arranged in rows and columns. Each of the multiplier cells outputs a sum and a product and each cell includes five inputs. The 1^st input receives a preceding cell's multiply output, the 2^nd input receives at least one bit of the 2^nd operand, the 3^rd input receives a preceding cell's sum output, a 4^th input receives at least one bit of the generating polynomial, and the 5^th input receives a feedback term from a preceding cell in a preceding row. The multiplier cells in the 1^st row have the 1^st input, 3^rd input, and 5^th input set to corresponding initialization values in accordance with the 2^nd operand.