Partial response receiver

摘要

The present invention relates to a clock data recovery circuit comprising a data sampling circuit to generate data samples of an input data signal in response to a first clock signal; an edge sampling circuit to generate edge samples of the input data signal in response to a second clock signal; and a clock recovery circuit coupled to receive the edge samples and the data samples, the clock recovery circuit being configured to adjust a phase of the second clock signal according to the state of one of the edge samples upon determining that a sequence of at least three of the data samples matches at least one sample pattern of a plurality of predetermined sample patterns.